How Peking University's analog solver earns its precision

PKU MEMLAB’s test board for high-precision matrix–vector multiplication, part of the 2025 solver experiment. Photograph: Zuo and colleagues, Supplementary Figure 7, Nature Electronics.[1]

A memory cell that distinguishes only eight electrical states sounds like an unlikely foundation for precise scientific computing. Yet a Peking University team used such devices in a system that experimentally inverted a 16 × 16 matrix with 24-bit fixed-point precision. The result, published on October 13, 2025, came from arranging imperfect calculations into a process that could correct itself.[1]

For China's AI computing research, the interesting advance sits between the device and the application. A useful accelerator needs a method for representing numbers, checking answers, and handling problems larger than its physical arrays. This experiment makes those layers unusually visible.

Give the rough answer a careful check

Resistive random-access memory, or RRAM, stores information through electrical conductance: how readily a device lets current pass. Arrays can encode a matrix and use electrical behavior to perform calculations. The attraction is that information can be processed where it is stored. The difficulty is obtaining a sufficiently accurate answer from physical components.[2]

The PKU approach pairs approximate matrix inversion with more accurate matrix–vector multiplication. The first operation supplies a correction; the second evaluates the error left behind. Repeating that sequence progressively improves the solution. For the multiplication, bit slicing distributes a number across lower-precision pieces whose results can be combined. The university reports a relative error around 10⁻⁷ after ten iterations in its matrix experiment.[2]

This is a useful way to think about the hardware: the precision of an individual memory cell and the precision of the completed calculation describe different things. The system earns the latter through additional work. Its efficiency depends on how much correction that work requires.

An older idea moves further into memory

Iterative correction already had a place in computing with imperfect devices. In 2018, IBM researchers demonstrated a mixed-precision design that assigned substantial calculation to computational memory while a conventional digital computer improved the answer. Their experiments included a system of 5,000 equations using almost a million phase-change memory devices.[3]

That precedent matters because it locates the engineering question. Once correction makes accurate results possible, designers can ask where each part of the correction should run. PKU's contribution places both the approximate inversion and the precise multiplication in analog matrix-computing hardware.[1] Moving those operations changes the architecture; it also makes the surrounding control and conversion circuitry part of the performance story.

A large problem can live on small arrays

Size poses another challenge. A larger memory array brings manufacturing constraints, circuit imperfections, and resistance in the wires connecting its cells. Simply enlarging a successful circuit can make its numerical behavior harder to control.[4]

The team's earlier BlockAMC work, posted in January 2024 and accepted at DATE that year, addressed this by dividing a large matrix into smaller blocks. Separate inversion and multiplication operations work on those blocks, then combine their partial solutions. Repeating the division allows a larger mathematical problem to fit smaller physical units.[4]

The practical idea is appealing: make the algorithm accommodate buildable hardware. The tradeoff is that partitioning introduces a sequence of operations. A fast individual calculation must therefore be assessed alongside the number of calculations needed to finish the problem. The 2025 precision experiment brought block processing into its demonstrated solver.[1]

Read the circuit boards alongside the speed claim

The supplementary photographs show a system still assembled from distinct parts. A PC coordinates experimental boards; approximate inversion uses an 8 × 8 RRAM array, while precise multiplication uses an integrated 1-Mb RRAM chip. The authors describe combining the functions and digital control into a future system-on-chip.[1]

That distinction becomes especially important in the performance comparison. The paper's largest gains—up to roughly 1,000-fold throughput and nearly 100-fold energy efficiency—come from projections, including larger arrays and faster circuits. GPU throughput is normalized to one core. The figures therefore do not establish a measured thousandfold speedup over a complete H100 running an AI application.[1]

The valuable result is more specific: a demonstrated route to accurate answers, plus a model of what further circuit improvements could deliver. Keeping those two achievements separate makes the research easier to build on.

Integration becomes the next test

A January 2026 paper by Piergiulio Mannocci and colleagues, including PKU's Zhong Sun, illustrates another step toward integration. That work uses SRAM rather than RRAM and puts two 64 × 64 arrays, feedback amplifiers, and converters on a 90-nanometer chip. Its demonstrations include differential equations, trajectory tracking, and robot-arm inverse kinematics.[5]

This is a separate design, with its own precision and workload boundaries. Its relevance is the direction of travel: more of the circuitry required to obtain a useful answer moves onto the chip. A convincing computing platform must make those supporting functions reproducible and manageable alongside the memory array.

The PKU study also makes figure data available through a public deposit.[6] That gives readers a way to examine the evidence behind its plots. The next questions I would ask are operational: how often must devices be programmed again, which matrices converge reliably, and how much time and energy does the complete system consume from input to accepted answer?

Those questions connect a laboratory result to the AI stack. The promise of analog computing grows when researchers can show where its errors go—and what it costs to remove them.

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